
module M28_AFE_TIMING(POWER_ON_DELAY, SYSTEM_CLK, INTEGRATE_CLK, JMP, JMP2,
      JMP3, DIO, V1_CLK, V2_CLK, H1_CLK, H1BR_CLK, H2_CLK, R_CLK, SHP, SHD,
      DATACLK, PBLK, CLPOB, CLPDM, VD, HD, PIX, FRAME, LINE, H2BR_CLK, FDG,
      V2B_CLK, CH1_SLOAD, CH2_SLOAD, SLOAD, SCLOCK, SERIAL_ENA, INTEGRATE,
      V3RD, V_SHUTTER, SER_CLK, load_byte, bit);


   input POWER_ON_DELAY, SYSTEM_CLK, INTEGRATE_CLK;
   input [1:0] JMP;
   input JMP2, JMP3;
   input [19:0] DIO;
   output V1_CLK, V2_CLK, H1_CLK, H1BR_CLK, H2_CLK, R_CLK, SHP, SHD, DATACLK,
	 PBLK, CLPOB, CLPDM, VD, HD, PIX, FRAME, LINE, H2BR_CLK, FDG, V2B_CLK,
	 CH1_SLOAD, CH2_SLOAD, SLOAD, SCLOCK, SERIAL_ENA, INTEGRATE, V3RD,
	 V_SHUTTER, SER_CLK, load_byte;
   output [7:0] bit;
   reg CLPOB;

 
   wire [11:0] H_XFER_COUNTER;
   wire [11:0] H_XFER_COUNTER_t;
   wire H_ENABLE_FF, H_ENABLE_FF_t, H_ENABLE_FF_clk, H_ENABLE_FF_clrn,
	 H_xfer_done_ff, H_xfer_done_ff_d, H_xfer_done_ff_clrn, H_xfer_done;
   wire [11:0] V_line_counter;
   wire [11:0] V_line_counter_d;
   wire frame_xfer_done_ff, frame_xfer_done_ff_d, frame_xfer_done_ff_clrn,
	 frame_xfer_done;
   wire [8:0] v_xfer_counter;
   wire [8:0] v_xfer_counter_d;
   wire v_xfer_done_ff, v_xfer_done_ff_d, v_xfer_done_ff_clrn, v_xfer_done,
	 V2_FF, V2_FF_clk, V2_FF_clrn, V1_FF, V1_FF_clk, V1_FF_clrn, V1_LINE,
	 V2_LINE;
   wire [2:0] cl;
   wire FRAME_FF, FRAME_FF_d, FRAME_FF_clk, FRAME_FF_clrn, FRAME_OUT_FF,
	 FRAME_OUT_FF_d, FRAME_OUT_FF_clk, FRAME_OUT_FF_clrn, LINE_FF,
	 LINE_FF_j, LINE_FF_clk, LINE_FF_clrn, power_on_clear, power_ff,
	 power_ff_d, power_ff_clk, power_ff_clrn, power_clear_ff1,
	 power_clear_ff1_d, power_clear_ff1_clk, power_clear_ff2,
	 power_clear_ff2_d, power_clear_ff2_clk, CLK_ENA_FF, CLK_ENA_FF_d,
	 CLK_ENA_FF_clk, CLK_ENA_FF_clrn, PIX_CLK_FF, PIX_CLK_FF_t,
	 PIX_CLK_FF_clk, PIX_CLK_FF_clrn, PIX_CLK_FF_ena, DELAYED_PIX_CLK_FF,
	 DELAYED_PIX_CLK_FF_t, DELAYED_PIX_CLK_FF_clk, DELAYED_PIX_CLK_FF_clrn,
	 DELAYED_PIX_CLK_FF_ena, DELAYED_PIXEL_CLK, PIXEL_CLK, update_byte;
   wire [5:0] control_clk;
   wire [5:0] control_clk_d;
   wire update_ff, update_ff_d, update_ff_clk, update_ff_clrn, load_ff,
	 load_ff_d, load_ff_clk, load_ff_clrn, sclock_ff, sclock_ff_d,
	 sclock_ff_clk, sclock_ff_clrn;
   wire [7:0] FF_BIT;
   wire [7:0] FF_BIT_d;
   wire SER_CLK_FF1, SER_CLK_FF1_t, SER_CLK_FF1_clk, SER_CLK_FF2,
	 SER_CLK_FF2_t, SER_CLK_FF2_clk, DEFAULT_AFE_FF, DEFAULT_AFE_FF_d,
	 DEFAULT_AFE_FF_clk, DEFAULT_AFE_FF_clrn;
   wire [1:0] DELAY_SLOAD_COUNTER;
   wire [1:0] DELAY_SLOAD_COUNTER_d;
   wire SLOAD_ENABLE_FF, SLOAD_ENABLE_FF_d, SLOAD_ENABLE_FF_clk,
	 SLOAD_ENABLE_FF_clrn, DEFAULT_DELAY_FF, DEFAULT_DELAY_FF_d,
	 DEFAULT_DELAY_FF_clk, DEFAULT_DELAY_FF_clrn, SLOAD_AFE_FF,
	 SLOAD_AFE_FF_j, SLOAD_AFE_FF_k, SLOAD_AFE_FF_clk, SLOAD_AFE_FF_clrn,
	 SLOAD_AFE_FF_ena, SCOUNTER_CLR_FF, SCOUNTER_CLR_FF_d,
	 SCOUNTER_CLR_FF_clk, SCOUNTER_CLR_FF_clrn, CLEAR_SCOUNTER_FF1,
	 CLEAR_SCOUNTER_FF1_d, CLEAR_SCOUNTER_FF1_clk, CLEAR_SCOUNTER_FF1_clrn,
	 CLEAR_SCOUNTER_FF2, CLEAR_SCOUNTER_FF2_d, CLEAR_SCOUNTER_FF2_clk,
	 SER_COUNTER_CLEAR, SLOAD_DELAY_FF, SLOAD_DELAY_FF_j, SLOAD_DELAY_FF_k,
	 SLOAD_DELAY_FF_clk, SLOAD_DELAY_FF_clrn, SLOAD_DELAY_FF_ena,
	 SLOAD_OK_FF, SLOAD_OK_FF_d, SLOAD_OK_FF_clk, SLOAD_OK_FF_clrn;
   wire [3:0] sclk;
   wire [4:0] AFE;
   wire PBLK_FF, PBLK_FF_clk, PBLK_FF_clrn, CLPOB1_ENA_FF, CLPOB1_ENA_FF_j,
	 CLPOB1_ENA_FF_k, CLPOB1_ENA_FF_clk, CLPOB1_ENA_FF_clrn, CLPOB1_FF,
	 CLPOB1_FF_j, CLPOB1_FF_k, CLPOB1_FF_clk, CLPOB1_FF_clrn, CLPOB1,
	 CLPOB2_FF, CLPOB2_FF_j, CLPOB2_FF_k, CLPOB2_FF_clk, CLPOB2_FF_clrn,
	 CLPOB2, CLPDM_FF, CLPDM_FF_j, CLPDM_FF_k, CLPDM_FF_clk, CLPDM_FF_clrn,
	 Acquire_ff, Acquire_ff_d, Acquire_ff_clk, Acquire_ff_clrn,
	 EXT_TRIG_OK, EXT_TRIG_FF, EXT_TRIG_FF_d, EXT_TRIG_FF_clk,
	 EXT_TRIG_FF_clrn, FLUSH_DONE, integrate_done, V1_FLUSH, V2_FLUSH;
   wire [8:0] V_FLUSH_COUNTER;
   wire [8:0] V_FLUSH_COUNTER_d;
   wire V1_FLUSH_FF, V1_FLUSH_FF_j, V1_FLUSH_FF_k, V1_FLUSH_FF_clk,
	 V1_FLUSH_FF_clrn, V1_FLUSH_FF_ena, V2_FLUSH_FF, V2_FLUSH_FF_j,
	 V2_FLUSH_FF_k, V2_FLUSH_FF_clk, V2_FLUSH_FF_clrn, V2_FLUSH_FF_ena;
   wire [11:0] flush_lines_counter;
   wire [11:0] flush_lines_counter_d;
   wire [15:0] integration_counter;
   wire [15:0] integration_counter_d;
   wire internal_integrate_done_ff, internal_integrate_done_ff_k,
	 internal_integrate_done_ff_clk, internal_integrate_done_ff_clrn,
	 external_integrate_done_ff, external_integrate_done_ff_d,
	 external_integrate_done_ff_clk, external_integrate_done_ff_clrn,
	 INTEGRATE_OK, INTEGRATE_OK_FF, INTEGRATE_OK_FF_d, INTEGRATE_OK_FF_clk,
	 INTEGRATE_OK_FF_clrn, INTEGRATE_OK_FF_ena, INTEGRATE_SYNC,
	 INTEGRATE_SYNC_d, INTEGRATE_SYNC_clk, INTEGRATE_SYNC_clrn, FLUSH_OK,
	 FLUSH_OK_FF, FLUSH_OK_FF_d, FLUSH_OK_FF_clk, FLUSH_OK_FF_clrn,
	 FLUSH1_FF, FLUSH1_FF_d, FLUSH1_FF_clk, FLUSH1_FF_clrn, FLUSH_INTERNAL;
   wire [2:0] INT_WAIT1_COUNTER;
   wire [2:0] INT_WAIT1_COUNTER_d;
   wire EXT_INT_FF, EXT_INT_FF_j, EXT_INT_FF_k, EXT_INT_FF_clk,
	 EXT_INT_FF_clrn, INT_WAIT_FF, INT_WAIT_FF_d, INT_WAIT_FF_clk,
	 INT_WAIT_FF_clrn;
   wire [2:0] INT_WAIT2_COUNTER;
   wire [2:0] INT_WAIT2_COUNTER_d;
   wire INT_END_FF, INT_END_FF_d, INT_END_FF_clk, INT_END_FF_clrn,
	 END_INTEGRATION;
   wire [9:0] INT_PULSE_COUNTER;
   wire [9:0] INT_PULSE_COUNTER_d;
   wire INT_PULSE_DONE_FF, INT_PULSE_DONE_FF_d, INT_PULSE_DONE_FF_clrn,
	 INT_PULSE_DONE, PULSE_INTEGRATE_FF, PULSE_INTEGRATE_FF_d,
	 PULSE_INTEGRATE_FF_clk, PULSE_INTEGRATE_FF_clrn, PULSE_INT_CLK_FF,
	 PULSE_INT_CLK_FF_t, PULSE_INT_CLK_FF_clk, PULSE_INT_CLK_FF_clrn,
	 PULSE_INT_CLK_FF_ena, PULSE_INT_CLK, lod_ff, lod_ff_j, lod_ff_k,
	 lod_ff_clk, lod_ff_clrn, vcc, gnd, AFE0_clk_ctrl, AFE0_clr_ctrl,
	 AFE0_ena_ctrl, sclk0_clk_ctrl, sclk0_clr_ctrl, FF_BIT0_clk_ctrl,
	 control_clk0_clrn_ctrl, control_clk0_ena_ctrl, control_clk0_clk_ctrl,
	 DELAY_SLOAD_COUNTER0_clk_ctrl, DELAY_SLOAD_COUNTER0_clrn_ctrl,
	 integration_counter0_clrn_ctrl, integration_counter0_ena_ctrl,
	 integration_counter0_clk_ctrl, V_line_counter0_clrn_ctrl,
	 V_line_counter0_ena_ctrl, V_line_counter0_clk_ctrl,
	 H_XFER_COUNTER0_clrn_ctrl, H_XFER_COUNTER0_ena_ctrl,
	 H_XFER_COUNTER0_clk_ctrl, flush_lines_counter0_clrn_ctrl,
	 flush_lines_counter0_ena_ctrl, flush_lines_counter0_clk_ctrl,
	 V_FLUSH_COUNTER0_clk_ctrl, V_FLUSH_COUNTER0_clrn_ctrl,
	 V_FLUSH_COUNTER0_ena_ctrl, v_xfer_counter0_clrn_ctrl,
	 v_xfer_counter0_ena_ctrl, v_xfer_counter0_clk_ctrl, cl0_clr_ctrl,
	 cl0_clk_ctrl, INT_PULSE_COUNTER0_clrn_ctrl,
	 INT_PULSE_COUNTER0_ena_ctrl, INT_PULSE_COUNTER0_clk_ctrl,
	 INT_WAIT2_COUNTER0_clrn_ctrl, INT_WAIT2_COUNTER0_ena_ctrl,
	 INT_WAIT2_COUNTER0_clk_ctrl, INT_WAIT1_COUNTER0_clrn_ctrl,
	 INT_WAIT1_COUNTER0_ena_ctrl, INT_WAIT1_COUNTER0_clk_ctrl;
   reg [11:0] H_XFER_COUNTER_q;
   reg H_ENABLE_FF_q, H_xfer_done_ff_clk, H_xfer_done_ff_q;
   reg [11:0] V_line_counter_q;
   reg frame_xfer_done_ff_clk, frame_xfer_done_ff_q;
   reg [8:0] v_xfer_counter_q;
   reg v_xfer_done_ff_clk, v_xfer_done_ff_q, V2_FF_j, V2_FF_k, V2_FF_q,
	 V1_FF_j, V1_FF_k, V1_FF_q;
   reg [2:0] cl_d;
   reg [2:0] cl_q;
   reg FRAME_FF_q, FRAME_OUT_FF_q, LINE_FF_k, LINE_FF_q, power_ff_q,
	 power_clear_ff1_q, power_clear_ff2_q, CLK_ENA_FF_q, PIX_CLK_FF_q,
	 DELAYED_PIX_CLK_FF_q;
   reg [5:0] control_clk_q;
   reg update_ff_q, load_ff_q, sclock_ff_q;
   reg [7:0] FF_BIT_q;
   reg SER_CLK_FF1_q, SER_CLK_FF2_q, DEFAULT_AFE_FF_q;
   reg [1:0] DELAY_SLOAD_COUNTER_q;
   reg SLOAD_ENABLE_FF_q, DEFAULT_DELAY_FF_q, SLOAD_AFE_FF_q,
	 SCOUNTER_CLR_FF_q, CLEAR_SCOUNTER_FF1_q, CLEAR_SCOUNTER_FF2_q,
	 SLOAD_DELAY_FF_q, SLOAD_OK_FF_q;
   reg [3:0] sclk_d;
   reg [3:0] sclk_q;
   reg [4:0] AFE_d;
   reg [4:0] AFE_q;
   reg PBLK_FF_j, PBLK_FF_k, PBLK_FF_q, CLPOB1_ENA_FF_q, CLPOB1_FF_q,
	 CLPOB2_FF_q, CLPDM_FF_q, Acquire_ff_q, EXT_TRIG_FF_q;
   reg [8:0] V_FLUSH_COUNTER_q;
   reg V1_FLUSH_FF_q, V2_FLUSH_FF_q;
   reg [11:0] flush_lines_counter_q;
   reg [15:0] integration_counter_q;
   reg internal_integrate_done_ff_j, internal_integrate_done_ff_q,
	 external_integrate_done_ff_q, INTEGRATE_OK_FF_q, INTEGRATE_SYNC_q,
	 FLUSH_OK_FF_q, FLUSH1_FF_q;
   reg [2:0] INT_WAIT1_COUNTER_q;
   reg EXT_INT_FF_q, INT_WAIT_FF_q;
   reg [2:0] INT_WAIT2_COUNTER_q;
   reg INT_END_FF_q;
   reg [9:0] INT_PULSE_COUNTER_q;
   reg INT_PULSE_DONE_FF_clk, INT_PULSE_DONE_FF_q, PULSE_INTEGRATE_FF_q,
	 PULSE_INTEGRATE, PULSE_INT_CLK_FF_q, lod_ff_q, FF_BIT0_d_1,
	 FF_BIT0_d_2, FF_BIT1_d_1, FF_BIT1_d_2, FF_BIT2_d_1, FF_BIT2_d_2,
	 FF_BIT3_d_1, FF_BIT3_d_2, FF_BIT4_d_1, FF_BIT4_d_2, FF_BIT5_d_1,
	 FF_BIT5_d_2, FF_BIT6_d_1, FF_BIT6_d_2, FF_BIT7_d_1, FF_BIT7_d_2;


   always @(posedge H_XFER_COUNTER0_clk_ctrl or negedge
	 H_XFER_COUNTER0_clrn_ctrl)
      if (!H_XFER_COUNTER0_clrn_ctrl)
	 H_XFER_COUNTER_q <= 12'h0;
      else
	 if (H_XFER_COUNTER0_ena_ctrl)
	    H_XFER_COUNTER_q <= H_XFER_COUNTER_q ^ H_XFER_COUNTER_t;

   always @(posedge H_ENABLE_FF_clk or negedge H_ENABLE_FF_clrn)
      if (!H_ENABLE_FF_clrn)
	 H_ENABLE_FF_q <= 1'h0;
      else
	 H_ENABLE_FF_q <= H_ENABLE_FF_q ^ H_ENABLE_FF_t;

   always @(posedge H_xfer_done_ff_clk or negedge H_xfer_done_ff_clrn)
      if (!H_xfer_done_ff_clrn)
	 H_xfer_done_ff_q <= 1'h0;
      else
	 H_xfer_done_ff_q <= H_xfer_done_ff_d;

   always @(posedge V_line_counter0_clk_ctrl or negedge
	 V_line_counter0_clrn_ctrl)
      if (!V_line_counter0_clrn_ctrl)
	 V_line_counter_q <= 12'h0;
      else
	 if (V_line_counter0_ena_ctrl)
	    V_line_counter_q <= V_line_counter_d;

   always @(posedge frame_xfer_done_ff_clk or negedge frame_xfer_done_ff_clrn)
      if (!frame_xfer_done_ff_clrn)
	 frame_xfer_done_ff_q <= 1'h0;
      else
	 frame_xfer_done_ff_q <= frame_xfer_done_ff_d;

   always @(posedge v_xfer_counter0_clk_ctrl or negedge
	 v_xfer_counter0_clrn_ctrl)
      if (!v_xfer_counter0_clrn_ctrl)
	 v_xfer_counter_q <= 9'h0;
      else
	 if (v_xfer_counter0_ena_ctrl)
	    v_xfer_counter_q <= v_xfer_counter_d;

   always @(posedge v_xfer_done_ff_clk or negedge v_xfer_done_ff_clrn)
      if (!v_xfer_done_ff_clrn)
	 v_xfer_done_ff_q <= 1'h0;
      else
	 v_xfer_done_ff_q <= v_xfer_done_ff_d;

   always @(posedge V2_FF_clk or negedge V2_FF_clrn)
      if (!V2_FF_clrn)
	 V2_FF_q <= 1'h0;
      else
	 V2_FF_q <= (V2_FF_q & ~(V2_FF_k))
	       | (~(V2_FF_q) & V2_FF_j)
	       | (V2_FF_j & ~(V2_FF_k));

   always @(posedge V1_FF_clk or negedge V1_FF_clrn)
      if (!V1_FF_clrn)
	 V1_FF_q <= 1'h0;
      else
	 V1_FF_q <= (V1_FF_q & ~(V1_FF_k))
	       | (~(V1_FF_q) & V1_FF_j)
	       | (V1_FF_j & ~(V1_FF_k));

   always @(posedge cl0_clk_ctrl or posedge cl0_clr_ctrl)
      if (cl0_clr_ctrl)
	 cl_q <= 3'h0;
      else
	 cl_q <= cl_d;

   always @(posedge FRAME_FF_clk or negedge FRAME_FF_clrn)
      if (!FRAME_FF_clrn)
	 FRAME_FF_q <= 1'h0;
      else
	 FRAME_FF_q <= FRAME_FF_d;

   always @(posedge FRAME_OUT_FF_clk or negedge FRAME_OUT_FF_clrn)
      if (!FRAME_OUT_FF_clrn)
	 FRAME_OUT_FF_q <= 1'h0;
      else
	 FRAME_OUT_FF_q <= FRAME_OUT_FF_d;

   always @(posedge LINE_FF_clk or negedge LINE_FF_clrn)
      if (!LINE_FF_clrn)
	 LINE_FF_q <= 1'h0;
      else
	 LINE_FF_q <= (LINE_FF_q & ~(LINE_FF_k))
	       | (~(LINE_FF_q) & LINE_FF_j)
	       | (LINE_FF_j & ~(LINE_FF_k));

   always @(posedge power_ff_clk or negedge power_ff_clrn)
      if (!power_ff_clrn)
	 power_ff_q <= 1'h0;
      else
	 power_ff_q <= power_ff_d;

   always @(posedge power_clear_ff1_clk)
      power_clear_ff1_q <= power_clear_ff1_d;

   always @(posedge power_clear_ff2_clk)
      power_clear_ff2_q <= power_clear_ff2_d;

   always @(posedge CLK_ENA_FF_clk or negedge CLK_ENA_FF_clrn)
      if (!CLK_ENA_FF_clrn)
	 CLK_ENA_FF_q <= 1'h0;
      else
	 CLK_ENA_FF_q <= CLK_ENA_FF_d;

   always @(posedge PIX_CLK_FF_clk or negedge PIX_CLK_FF_clrn)
      if (!PIX_CLK_FF_clrn)
	 PIX_CLK_FF_q <= 1'h0;
      else
	 if (PIX_CLK_FF_ena)
	    PIX_CLK_FF_q <= PIX_CLK_FF_q ^ PIX_CLK_FF_t;

   always @(posedge DELAYED_PIX_CLK_FF_clk or negedge DELAYED_PIX_CLK_FF_clrn)
      if (!DELAYED_PIX_CLK_FF_clrn)
	 DELAYED_PIX_CLK_FF_q <= 1'h0;
      else
	 if (DELAYED_PIX_CLK_FF_ena)
	    DELAYED_PIX_CLK_FF_q <= DELAYED_PIX_CLK_FF_q ^
		  DELAYED_PIX_CLK_FF_t;

   always @(posedge control_clk0_clk_ctrl or negedge control_clk0_clrn_ctrl)
      if (!control_clk0_clrn_ctrl)
	 control_clk_q <= 6'h0;
      else
	 if (control_clk0_ena_ctrl)
	    control_clk_q <= control_clk_d;

   always @(posedge update_ff_clk or negedge update_ff_clrn)
      if (!update_ff_clrn)
	 update_ff_q <= 1'h0;
      else
	 update_ff_q <= update_ff_d;

   always @(posedge load_ff_clk or negedge load_ff_clrn)
      if (!load_ff_clrn)
	 load_ff_q <= 1'h0;
      else
	 load_ff_q <= load_ff_d;

   always @(posedge sclock_ff_clk or negedge sclock_ff_clrn)
      if (!sclock_ff_clrn)
	 sclock_ff_q <= 1'h0;
      else
	 sclock_ff_q <= sclock_ff_d;

   always @(posedge FF_BIT0_clk_ctrl)
      FF_BIT_q <= FF_BIT_d;

   always @(posedge SER_CLK_FF1_clk)
      SER_CLK_FF1_q <= SER_CLK_FF1_q ^ SER_CLK_FF1_t;

   always @(posedge SER_CLK_FF2_clk)
      SER_CLK_FF2_q <= SER_CLK_FF2_q ^ SER_CLK_FF2_t;

   always @(posedge DEFAULT_AFE_FF_clk or negedge DEFAULT_AFE_FF_clrn)
      if (!DEFAULT_AFE_FF_clrn)
	 DEFAULT_AFE_FF_q <= 1'h0;
      else
	 DEFAULT_AFE_FF_q <= DEFAULT_AFE_FF_d;

   always @(posedge DELAY_SLOAD_COUNTER0_clk_ctrl or negedge
	 DELAY_SLOAD_COUNTER0_clrn_ctrl)
      if (!DELAY_SLOAD_COUNTER0_clrn_ctrl)
	 DELAY_SLOAD_COUNTER_q <= 2'h0;
      else
	 DELAY_SLOAD_COUNTER_q <= DELAY_SLOAD_COUNTER_d;

   always @(posedge SLOAD_ENABLE_FF_clk or negedge SLOAD_ENABLE_FF_clrn)
      if (!SLOAD_ENABLE_FF_clrn)
	 SLOAD_ENABLE_FF_q <= 1'h0;
      else
	 SLOAD_ENABLE_FF_q <= SLOAD_ENABLE_FF_d;

   always @(posedge DEFAULT_DELAY_FF_clk or negedge DEFAULT_DELAY_FF_clrn)
      if (!DEFAULT_DELAY_FF_clrn)
	 DEFAULT_DELAY_FF_q <= 1'h0;
      else
	 DEFAULT_DELAY_FF_q <= DEFAULT_DELAY_FF_d;

   always @(posedge SLOAD_AFE_FF_clk or negedge SLOAD_AFE_FF_clrn)
      if (!SLOAD_AFE_FF_clrn)
	 SLOAD_AFE_FF_q <= 1'h0;
      else
	 if (SLOAD_AFE_FF_ena)
	    SLOAD_AFE_FF_q <= (SLOAD_AFE_FF_q & ~(SLOAD_AFE_FF_k))
		  | (~(SLOAD_AFE_FF_q) & SLOAD_AFE_FF_j)
		  | (SLOAD_AFE_FF_j & ~(SLOAD_AFE_FF_k));

   always @(posedge SCOUNTER_CLR_FF_clk or negedge SCOUNTER_CLR_FF_clrn)
      if (!SCOUNTER_CLR_FF_clrn)
	 SCOUNTER_CLR_FF_q <= 1'h0;
      else
	 SCOUNTER_CLR_FF_q <= SCOUNTER_CLR_FF_d;

   always @(posedge CLEAR_SCOUNTER_FF1_clk or negedge CLEAR_SCOUNTER_FF1_clrn)
      if (!CLEAR_SCOUNTER_FF1_clrn)
	 CLEAR_SCOUNTER_FF1_q <= 1'h0;
      else
	 CLEAR_SCOUNTER_FF1_q <= CLEAR_SCOUNTER_FF1_d;

   always @(posedge CLEAR_SCOUNTER_FF2_clk)
      CLEAR_SCOUNTER_FF2_q <= CLEAR_SCOUNTER_FF2_d;

   always @(posedge SLOAD_DELAY_FF_clk or negedge SLOAD_DELAY_FF_clrn)
      if (!SLOAD_DELAY_FF_clrn)
	 SLOAD_DELAY_FF_q <= 1'h0;
      else
	 if (SLOAD_DELAY_FF_ena)
	    SLOAD_DELAY_FF_q <= (SLOAD_DELAY_FF_q & ~(SLOAD_DELAY_FF_k))
		  | (~(SLOAD_DELAY_FF_q) & SLOAD_DELAY_FF_j)
		  | (SLOAD_DELAY_FF_j & ~(SLOAD_DELAY_FF_k));

   always @(posedge SLOAD_OK_FF_clk or negedge SLOAD_OK_FF_clrn)
      if (!SLOAD_OK_FF_clrn)
	 SLOAD_OK_FF_q <= 1'h0;
      else
	 SLOAD_OK_FF_q <= SLOAD_OK_FF_d;

   always @(posedge sclk0_clk_ctrl or posedge sclk0_clr_ctrl)
      if (sclk0_clr_ctrl)
	 sclk_q <= 4'h0;
      else
	 sclk_q <= sclk_d;

   always @(posedge AFE0_clk_ctrl or posedge AFE0_clr_ctrl)
      if (AFE0_clr_ctrl)
	 AFE_q <= 5'h0;
      else
	 if (AFE0_ena_ctrl)
	    AFE_q <= AFE_d;

   always @(posedge PBLK_FF_clk or negedge PBLK_FF_clrn)
      if (!PBLK_FF_clrn)
	 PBLK_FF_q <= 1'h0;
      else
	 PBLK_FF_q <= (PBLK_FF_q & ~(PBLK_FF_k))
	       | (~(PBLK_FF_q) & PBLK_FF_j)
	       | (PBLK_FF_j & ~(PBLK_FF_k));

   always @(posedge CLPOB1_ENA_FF_clk or negedge CLPOB1_ENA_FF_clrn)
      if (!CLPOB1_ENA_FF_clrn)
	 CLPOB1_ENA_FF_q <= 1'h0;
      else
	 CLPOB1_ENA_FF_q <= (CLPOB1_ENA_FF_q & ~(CLPOB1_ENA_FF_k))
	       | (~(CLPOB1_ENA_FF_q) & CLPOB1_ENA_FF_j)
	       | (CLPOB1_ENA_FF_j & ~(CLPOB1_ENA_FF_k));

   always @(posedge CLPOB1_FF_clk or negedge CLPOB1_FF_clrn)
      if (!CLPOB1_FF_clrn)
	 CLPOB1_FF_q <= 1'h0;
      else
	 CLPOB1_FF_q <= (CLPOB1_FF_q & ~(CLPOB1_FF_k))
	       | (~(CLPOB1_FF_q) & CLPOB1_FF_j)
	       | (CLPOB1_FF_j & ~(CLPOB1_FF_k));

   always @(posedge CLPOB2_FF_clk or negedge CLPOB2_FF_clrn)
      if (!CLPOB2_FF_clrn)
	 CLPOB2_FF_q <= 1'h0;
      else
	 CLPOB2_FF_q <= (CLPOB2_FF_q & ~(CLPOB2_FF_k))
	       | (~(CLPOB2_FF_q) & CLPOB2_FF_j)
	       | (CLPOB2_FF_j & ~(CLPOB2_FF_k));

   always @(posedge CLPDM_FF_clk or negedge CLPDM_FF_clrn)
      if (!CLPDM_FF_clrn)
	 CLPDM_FF_q <= 1'h0;
      else
	 CLPDM_FF_q <= (CLPDM_FF_q & ~(CLPDM_FF_k))
	       | (~(CLPDM_FF_q) & CLPDM_FF_j)
	       | (CLPDM_FF_j & ~(CLPDM_FF_k));

   always @(posedge Acquire_ff_clk or negedge Acquire_ff_clrn)
      if (!Acquire_ff_clrn)
	 Acquire_ff_q <= 1'h0;
      else
	 Acquire_ff_q <= Acquire_ff_d;

   always @(posedge EXT_TRIG_FF_clk or negedge EXT_TRIG_FF_clrn)
      if (!EXT_TRIG_FF_clrn)
	 EXT_TRIG_FF_q <= 1'h0;
      else
	 EXT_TRIG_FF_q <= EXT_TRIG_FF_d;

   always @(posedge V_FLUSH_COUNTER0_clk_ctrl or negedge
	 V_FLUSH_COUNTER0_clrn_ctrl)
      if (!V_FLUSH_COUNTER0_clrn_ctrl)
	 V_FLUSH_COUNTER_q <= 9'h0;
      else
	 if (V_FLUSH_COUNTER0_ena_ctrl)
	    V_FLUSH_COUNTER_q <= V_FLUSH_COUNTER_d;

   always @(posedge V1_FLUSH_FF_clk or negedge V1_FLUSH_FF_clrn)
      if (!V1_FLUSH_FF_clrn)
	 V1_FLUSH_FF_q <= 1'h0;
      else
	 if (V1_FLUSH_FF_ena)
	    V1_FLUSH_FF_q <= (V1_FLUSH_FF_q & ~(V1_FLUSH_FF_k))
		  | (~(V1_FLUSH_FF_q) & V1_FLUSH_FF_j)
		  | (V1_FLUSH_FF_j & ~(V1_FLUSH_FF_k));

   always @(posedge V2_FLUSH_FF_clk or negedge V2_FLUSH_FF_clrn)
      if (!V2_FLUSH_FF_clrn)
	 V2_FLUSH_FF_q <= 1'h0;
      else
	 if (V2_FLUSH_FF_ena)
	    V2_FLUSH_FF_q <= (V2_FLUSH_FF_q & ~(V2_FLUSH_FF_k))
		  | (~(V2_FLUSH_FF_q) & V2_FLUSH_FF_j)
		  | (V2_FLUSH_FF_j & ~(V2_FLUSH_FF_k));

   always @(posedge flush_lines_counter0_clk_ctrl or negedge
	 flush_lines_counter0_clrn_ctrl)
      if (!flush_lines_counter0_clrn_ctrl)
	 flush_lines_counter_q <= 12'h0;
      else
	 if (flush_lines_counter0_ena_ctrl)
	    flush_lines_counter_q <= flush_lines_counter_d;

   always @(posedge integration_counter0_clk_ctrl or negedge
	 integration_counter0_clrn_ctrl)
      if (!integration_counter0_clrn_ctrl)
	 integration_counter_q <= 16'h0;
      else
	 if (integration_counter0_ena_ctrl)
	    integration_counter_q <= integration_counter_d;

   always @(posedge internal_integrate_done_ff_clk or negedge
	 internal_integrate_done_ff_clrn)
      if (!internal_integrate_done_ff_clrn)
	 internal_integrate_done_ff_q <= 1'h0;
      else
	 internal_integrate_done_ff_q <= (internal_integrate_done_ff_q &
	       ~(internal_integrate_done_ff_k))
	       | (~(internal_integrate_done_ff_q) &
		     internal_integrate_done_ff_j)
	       | (internal_integrate_done_ff_j &
		     ~(internal_integrate_done_ff_k));

   always @(posedge external_integrate_done_ff_clk or negedge
	 external_integrate_done_ff_clrn)
      if (!external_integrate_done_ff_clrn)
	 external_integrate_done_ff_q <= 1'h0;
      else
	 external_integrate_done_ff_q <= external_integrate_done_ff_d;

   always @(posedge INTEGRATE_OK_FF_clk or negedge INTEGRATE_OK_FF_clrn)
      if (!INTEGRATE_OK_FF_clrn)
	 INTEGRATE_OK_FF_q <= 1'h0;
      else
	 if (INTEGRATE_OK_FF_ena)
	    INTEGRATE_OK_FF_q <= INTEGRATE_OK_FF_d;

   always @(posedge INTEGRATE_SYNC_clk or negedge INTEGRATE_SYNC_clrn)
      if (!INTEGRATE_SYNC_clrn)
	 INTEGRATE_SYNC_q <= 1'h0;
      else
	 INTEGRATE_SYNC_q <= INTEGRATE_SYNC_d;

   always @(posedge FLUSH_OK_FF_clk or negedge FLUSH_OK_FF_clrn)
      if (!FLUSH_OK_FF_clrn)
	 FLUSH_OK_FF_q <= 1'h0;
      else
	 FLUSH_OK_FF_q <= FLUSH_OK_FF_d;

   always @(posedge FLUSH1_FF_clk or negedge FLUSH1_FF_clrn)
      if (!FLUSH1_FF_clrn)
	 FLUSH1_FF_q <= 1'h0;
      else
	 FLUSH1_FF_q <= FLUSH1_FF_d;

   always @(posedge INT_WAIT1_COUNTER0_clk_ctrl or negedge
	 INT_WAIT1_COUNTER0_clrn_ctrl)
      if (!INT_WAIT1_COUNTER0_clrn_ctrl)
	 INT_WAIT1_COUNTER_q <= 3'h0;
      else
	 if (INT_WAIT1_COUNTER0_ena_ctrl)
	    INT_WAIT1_COUNTER_q <= INT_WAIT1_COUNTER_d;

   always @(posedge EXT_INT_FF_clk or negedge EXT_INT_FF_clrn)
      if (!EXT_INT_FF_clrn)
	 EXT_INT_FF_q <= 1'h0;
      else
	 EXT_INT_FF_q <= (EXT_INT_FF_q & ~(EXT_INT_FF_k))
	       | (~(EXT_INT_FF_q) & EXT_INT_FF_j)
	       | (EXT_INT_FF_j & ~(EXT_INT_FF_k));

   always @(posedge INT_WAIT_FF_clk or negedge INT_WAIT_FF_clrn)
      if (!INT_WAIT_FF_clrn)
	 INT_WAIT_FF_q <= 1'h0;
      else
	 INT_WAIT_FF_q <= INT_WAIT_FF_d;

   always @(posedge INT_WAIT2_COUNTER0_clk_ctrl or negedge
	 INT_WAIT2_COUNTER0_clrn_ctrl)
      if (!INT_WAIT2_COUNTER0_clrn_ctrl)
	 INT_WAIT2_COUNTER_q <= 3'h0;
      else
	 if (INT_WAIT2_COUNTER0_ena_ctrl)
	    INT_WAIT2_COUNTER_q <= INT_WAIT2_COUNTER_d;

   always @(posedge INT_END_FF_clk or negedge INT_END_FF_clrn)
      if (!INT_END_FF_clrn)
	 INT_END_FF_q <= 1'h0;
      else
	 INT_END_FF_q <= INT_END_FF_d;

   always @(posedge INT_PULSE_COUNTER0_clk_ctrl or negedge
	 INT_PULSE_COUNTER0_clrn_ctrl)
      if (!INT_PULSE_COUNTER0_clrn_ctrl)
	 INT_PULSE_COUNTER_q <= 10'h0;
      else
	 if (INT_PULSE_COUNTER0_ena_ctrl)
	    INT_PULSE_COUNTER_q <= INT_PULSE_COUNTER_d;

   always @(posedge INT_PULSE_DONE_FF_clk or negedge INT_PULSE_DONE_FF_clrn)
      if (!INT_PULSE_DONE_FF_clrn)
	 INT_PULSE_DONE_FF_q <= 1'h0;
      else
	 INT_PULSE_DONE_FF_q <= INT_PULSE_DONE_FF_d;

   always @(posedge PULSE_INTEGRATE_FF_clk or negedge PULSE_INTEGRATE_FF_clrn)
      if (!PULSE_INTEGRATE_FF_clrn)
	 PULSE_INTEGRATE_FF_q <= 1'h0;
      else
	 PULSE_INTEGRATE_FF_q <= PULSE_INTEGRATE_FF_d;

   always @(posedge PULSE_INT_CLK_FF_clk or negedge PULSE_INT_CLK_FF_clrn)
      if (!PULSE_INT_CLK_FF_clrn)
	 PULSE_INT_CLK_FF_q <= 1'h0;
      else
	 if (PULSE_INT_CLK_FF_ena)
	    PULSE_INT_CLK_FF_q <= PULSE_INT_CLK_FF_q ^ PULSE_INT_CLK_FF_t;

   always @(posedge lod_ff_clk or negedge lod_ff_clrn)
      if (!lod_ff_clrn)
	 lod_ff_q <= 1'h0;
      else
	 lod_ff_q <= (lod_ff_q & ~(lod_ff_k))
	       | (~(lod_ff_q) & lod_ff_j)
	       | (lod_ff_j & ~(lod_ff_k));

// Start of original equations

//  ****************************************************************** 
//  NOT USED 
   assign V3RD = vcc;

//  NOT USED 
   assign V_SHUTTER = vcc;

//  NOT USED 
   assign FDG = gnd;

//  NOT USED 
   assign VD = vcc;

//  NOT USED 
   assign HD = vcc;

//  NOT USED
   assign V2B_CLK = vcc;

//  V2B_CLK  =   !DIO13; -- V2B CONNECTED TO AMP_ENABLE; COULD
//  ****************************************************************** 
   assign lod_ff_clk = PIXEL_CLK;
   assign lod_ff_clrn = !(cl_q == 3'b000);
   assign lod_ff_j = integration_counter_q == 16'hA;
   assign lod_ff_k = v_xfer_done;
   assign H2BR_CLK = !(lod_ff_q & DIO[12]);

//  CLEAR ALL PLD FLIPFLOPS AT POWER UP OR PRESS OF BOARD_RESET BUTTON 
   assign power_ff_clk = POWER_ON_DELAY;
   assign power_ff_d = vcc;
   assign power_ff_clrn = !power_on_clear;
   assign power_clear_ff1_clk = SYSTEM_CLK;
   assign power_clear_ff1_d = power_ff_q;
   assign power_clear_ff2_clk = SYSTEM_CLK;
   assign power_clear_ff2_d = power_clear_ff1_q;
   assign power_on_clear = power_clear_ff2_q;
   assign CLK_ENA_FF_clk = !SYSTEM_CLK;
   assign CLK_ENA_FF_clrn = !power_on_clear;
   assign CLK_ENA_FF_d = vcc;
   assign PIX_CLK_FF_ena = CLK_ENA_FF_q;
   assign PIX_CLK_FF_clrn = !power_on_clear;
   assign PIX_CLK_FF_clk = SYSTEM_CLK;
   assign PIX_CLK_FF_t = vcc;
   assign PIXEL_CLK = PIX_CLK_FF_q;
   assign DELAYED_PIX_CLK_FF_ena = CLK_ENA_FF_q;
   assign DELAYED_PIX_CLK_FF_clrn = !power_on_clear;
   assign DELAYED_PIX_CLK_FF_clk = !SYSTEM_CLK;
   assign DELAYED_PIX_CLK_FF_t = vcc;
   assign DELAYED_PIXEL_CLK = DELAYED_PIX_CLK_FF_q;
   assign Acquire_ff_clk = !DIO[12];
   assign Acquire_ff_d = vcc;
   assign Acquire_ff_clrn = !(cl_q == 3'b000);

//  SYNCHRONIZE THE INTEGRATE_CLK WITH PIXEL_CLK
   assign INTEGRATE_SYNC_clk = PIXEL_CLK;
   assign INTEGRATE_SYNC_d = INTEGRATE_CLK;
   assign INTEGRATE_SYNC_clrn = !(cl_q == 3'b000);
   assign EXT_TRIG_FF_clk = INTEGRATE_SYNC_q;
   assign EXT_TRIG_FF_d = Acquire_ff_q;
   assign EXT_TRIG_FF_clrn = !(cl_q == 3'b000);
   assign EXT_TRIG_OK = EXT_TRIG_FF_q;

//  ****************************************************************
//  INT WAIT 1 COUNTER USED TO SET THE DELAY FROM WHEN THE STATE MACHINE ENTERS
//  THE INTEGRATION STATE AND WHEN THE INTEGRATION SIGNAL SENT OFF THE BOARD CAN GO HIGH
   assign INT_WAIT1_COUNTER0_clk_ctrl = INTEGRATE_SYNC_q;
   assign INT_WAIT1_COUNTER0_ena_ctrl = cl_q == 3'b100;
   assign INT_WAIT1_COUNTER0_clrn_ctrl = (!(cl_q == 3'b000)) &
	 (!integrate_done);
   assign INT_WAIT1_COUNTER_d = INT_WAIT1_COUNTER_q + 3'b001;

//  WHEN EXT_INT_FF GOES HIGH THE WAIT 1 DELAY IS OVER, INTEGRATION SIGNAL SENT OFF THE BOARD CAN GO HIGH
   assign EXT_INT_FF_clk = INTEGRATE_SYNC_q;
   assign EXT_INT_FF_clrn = !(cl_q == 3'b000);
   assign EXT_INT_FF_j = INT_WAIT1_COUNTER_q == 3'b001;
   assign EXT_INT_FF_k = integrate_done;

//  WHEN INT_WAIT_FF GOES HIGH, THE INTEGRATION TIME IS OVER, INTEGRATION SIGNAL SENT OFF THE BOARD GOES LOW
   assign INT_WAIT_FF_clk = integrate_done;
   assign INT_WAIT_FF_clrn = (!(cl_q == 3'b000)) & (!INT_END_FF_q);
   assign INT_WAIT_FF_d = vcc;

//  INT WAIT 2 COUNTER USED TO SET THE DELAY FROM WHEN THE INTEGRATION SIGNAL SENT OFF THE BOARD GOES LOW
//  AND WHEN THE STATE MACHINE ACTUALLY LEAVES THE INTEGRATION STATE
   assign INT_WAIT2_COUNTER0_clk_ctrl = INTEGRATE_SYNC_q;
   assign INT_WAIT2_COUNTER0_ena_ctrl = INT_WAIT_FF_q;
   assign INT_WAIT2_COUNTER0_clrn_ctrl = (!(cl_q == 3'b000)) & (!INT_END_FF_q);
   assign INT_WAIT2_COUNTER_d = INT_WAIT2_COUNTER_q + 3'b001;

//  END_INTEGRATION IS WHAT TRIGGERS THE STATE MACHINE TO MOVE ON TO THE NEXT STATE
   assign INT_END_FF_clk = INTEGRATE_SYNC_q;
   assign INT_END_FF_clrn = !(cl_q == 3'b000);
   assign INT_END_FF_d = INT_WAIT2_COUNTER_q == 3'b001;
   assign END_INTEGRATION = INT_END_FF_q;
   assign INT_PULSE_COUNTER0_clk_ctrl = INTEGRATE_SYNC_q;
   assign INT_PULSE_COUNTER0_ena_ctrl = EXT_INT_FF_q;
   assign INT_PULSE_COUNTER0_clrn_ctrl = !(cl_q == 3'b000);
   assign INT_PULSE_COUNTER_d = INT_PULSE_COUNTER_q + 10'b00_0000_0001;
   assign INT_PULSE_DONE_FF_d = vcc;
   assign INT_PULSE_DONE_FF_clrn = !(cl_q == 3'b000);
   assign INT_PULSE_DONE = INT_PULSE_DONE_FF_q;


   always @(DIO or INT_PULSE_COUNTER_q) begin
      INT_PULSE_DONE_FF_clk = 1'bx;

//  SET TO 2X THE DESIRED NUMBER OF PULSES (1/2 FREQUENCY PULSED INT CLOCK WITH 50% DUTY CYCLE)
      casex (DIO[5:2])
      4'b0000: begin

// DOESN'T MATTER
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_0001;
	 end
      4'b1111: begin

// DOESN'T MATTER
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_0001;
	 end
      4'b0001: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_0010;
	 end
      4'b0010: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_0100;
	 end
      4'b0011: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_0110;
	 end
      4'b0100: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_1000;
	 end
      4'b0101: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0000_1010;
	 end
      4'b0110: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0001_0100;
	 end
      4'b0111: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0010_1000;
	 end
      4'b1000: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0011_1100;
	 end
      4'b1001: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0101_0000;
	 end
      4'b1010: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_0110_0100;
	 end
      4'b1011: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_1001_0110;
	 end
      4'b1100: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b00_1100_1000;
	 end
      4'b1101: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b01_0010_1100;
	 end
      4'b1110: begin
	    INT_PULSE_DONE_FF_clk = INT_PULSE_COUNTER_q == 10'b01_1001_0000;
	 end
      endcase
   end
   assign PULSE_INTEGRATE_FF_clk = INTEGRATE_SYNC_q;
   assign PULSE_INTEGRATE_FF_clrn = !(cl_q == 3'b000);
   assign PULSE_INTEGRATE_FF_d = EXT_INT_FF_q & (!INT_PULSE_DONE);

// USE THIS FF TO GENERATE 2MS PERIOD 50% DUTY CYCLE PULSED LED PULSE
   assign PULSE_INT_CLK_FF_clk = INTEGRATE_SYNC_q;
   assign PULSE_INT_CLK_FF_clrn = !(cl_q == 3'b000);
   assign PULSE_INT_CLK_FF_ena = EXT_INT_FF_q;
   assign PULSE_INT_CLK_FF_t = vcc;
   assign PULSE_INT_CLK = PULSE_INT_CLK_FF_q;


   always @(DIO or gnd or EXT_INT_FF_q or integrate_done or PULSE_INT_CLK or
	 PULSE_INTEGRATE_FF_q) begin
      PULSE_INTEGRATE = 1'b0;
      casex (DIO[5:2])
      4'b1111: begin
	    PULSE_INTEGRATE = gnd;
	 end
      4'b0000: begin

// DEFAULT
	    PULSE_INTEGRATE = EXT_INT_FF_q & (!integrate_done);
	 end
      default: begin
	    PULSE_INTEGRATE = PULSE_INT_CLK & PULSE_INTEGRATE_FF_q;
	 end
      endcase
   end

//  Generate LED/shutter Sync signal %
//  INTEGRATE Output Indicates the integration time period
//  Can be used to syncronize LED's, or a shutter
   assign INTEGRATE = PULSE_INTEGRATE;

//  ******************************************************************
//  Clocking State Machine
//  This State Machine controls the overall flow of the timing
//  The state machine is reset upon power up or pressing of the Board_Reset button
   assign cl0_clk_ctrl = PIXEL_CLK;
   assign cl0_clr_ctrl = power_on_clear | DIO[11];


   always @(cl_q or AFE_q or EXT_TRIG_OK or JMP or INTEGRATE_OK or FLUSH_OK or
	 END_INTEGRATION or v_xfer_done or H_xfer_done or frame_xfer_done)
	 begin
      cl_d = cl_q;
      casex (cl_q)
      3'b000: begin
	    cl_d = 3'b001;
	 end
      3'b001: begin
	    cl_d = 3'b010;
	 end
      3'b010: begin
	    if (AFE_q == 5'b1_0010) begin

//  IN STILL MODE ONLY, MUST FLUSH CCD UPON RECEIVING ACQUIRE SIGNAL
	       if (JMP[1] & (!JMP[0])) begin

//  STILL MODE, EXT TRIGGER REQUIRED --
		  if (EXT_TRIG_OK) begin
		     cl_d = 3'b011;
		  end else begin
		     cl_d = 3'b010;
		  end
	       end

//  STILL_RUN MODE, EXT TRIGGER NOT REQUIRED --
	       if (JMP[1] & JMP[0]) begin
		  cl_d = 3'b011;
	       end

//  FREE_RUN MODE --
	       if (!JMP[1]) begin

//  KEEP IN SYNC WITH INTEGRATE CLK TO KEEP INTEGRATION TIMES CONSISTENT
		  if (INTEGRATE_OK) begin

//  NO FLUSH REQUIRED IN FREE-RUNNING MODE
		     cl_d = 3'b100;
		  end else begin
		     cl_d = 3'b010;
		  end
	       end
	    end else begin
	       cl_d = 3'b010;
	    end
	 end
      3'b011: begin

//  FLUSH THE CCD OF ANY ACCUMULATED CHARGE (DARK CURRENT)
//  WAIT UNTIL FLUSH IS COMPLETED BEFORE BEGINNING INTEGRATION
//  KEEP IN SYNC WITH INTEGRATE CLK TO KEEP INTEGRATION TIMES CONSISTENT
	    if (FLUSH_OK) begin
	       cl_d = 3'b100;
	    end else begin
	       cl_d = 3'b011;
	    end
	 end
      3'b100: begin

//  CCD IS EXPOSED TO LIGHT (OPEN SHUTTER OR STROBE LED'S)
//  REMAIN IN INTEGRATE STATE UNTIL END_INTEGRATION
	    if (END_INTEGRATION) begin

//  DEPENDENT UPON INTEGRATION MODE SELECTED
	       cl_d = 3'b101;
	    end else begin
	       cl_d = 3'b100;
	    end
	 end
      3'b101: begin

//  TRANSFER A LINE OF CHARGE ONTO THE CCD'S HORIZONTAL REGISTER
//  V_XFER_DONE INDICATES THE END OF THE VERTICAL TRANSFER
	    if (v_xfer_done) begin
	       cl_d = 3'b110;
	    end else begin
	       cl_d = 3'b101;
	    end
	 end
      3'b110: begin

//  TRANSFER THE LINE OF CHARGE TO THE OUTPUT OF THE CCD, PIXEL BY PIXEL
//  H_XFER_DONE INDICATES THE END OF THE LINE
	    if (H_xfer_done) begin
	       cl_d = 3'b111;
	    end else begin
	       cl_d = 3'b110;
	    end
	 end
      3'b111: begin

//  AT THE END OF A LINE, CHECK TO SEE IF LAST LINE OF CCD ARRAY
//  FRAME_XFER_DONE INDICATES THE END OF A FRAME
//  IF LAST LINE, GO BACK TO BEGINNING OF THE CYCLE
	    if (frame_xfer_done) begin
	       cl_d = 3'b000;
	    end else begin

//  IF NOT LAST LINE, GO BACK AND TRANSFER ANOTHER LINE
	       cl_d = 3'b101;
	    end
	 end
      default: begin
	    cl_d = 3'b000;
	 end
      endcase
   end
   assign v_xfer_counter0_clk_ctrl = PIXEL_CLK;
   assign v_xfer_counter0_ena_ctrl = cl_q == 3'b101;
   assign v_xfer_counter_d = v_xfer_counter_q + 9'b0_0000_0001;
   assign v_xfer_counter0_clrn_ctrl = !(cl_q == 3'b110);

//  V_XFER_DONE INDICATES THE END OF A VERTICAL TRANSFER
   assign v_xfer_done_ff_d = vcc;
   assign v_xfer_done_ff_clrn = (!(cl_q == 3'b001)) & (!(cl_q == 3'b110));


   always @(JMP3 or v_xfer_counter_q) begin
      v_xfer_done_ff_clk = 1'bx;
      if (JMP3) begin
	 v_xfer_done_ff_clk = v_xfer_counter_q == 9'b1_0001_1010;
      end else begin
	 v_xfer_done_ff_clk = v_xfer_counter_q == 9'b0_1111_1110;
      end
   end
   assign v_xfer_done = v_xfer_done_ff_q;

//  **********************************************
//  THE V_FLUSH_COUNTER IS USED TO GENERATE V1 AND V2 DURING THE STILL MODE FLUSH CYCLE
   assign FLUSH_INTERNAL = cl_q == 3'b011 & (!FLUSH_DONE);
   assign V_FLUSH_COUNTER0_ena_ctrl = FLUSH_INTERNAL;
   assign V_FLUSH_COUNTER0_clrn_ctrl = (!(cl_q == 3'b000)) &
	 (!(V_FLUSH_COUNTER_q == 9'b0_1110_0100));
   assign V_FLUSH_COUNTER0_clk_ctrl = PIXEL_CLK;
   assign V_FLUSH_COUNTER_d = V_FLUSH_COUNTER_q + 9'b0_0000_0001;
   assign V1_FLUSH_FF_clk = PIXEL_CLK;
   assign V1_FLUSH_FF_ena = FLUSH_INTERNAL;
   assign V1_FLUSH_FF_clrn = !(cl_q == 3'b000);
   assign V1_FLUSH_FF_j = V_FLUSH_COUNTER_q == 9'b0_0000_0010;
   assign V1_FLUSH_FF_k = V_FLUSH_COUNTER_q == 9'b0_1001_0000;
   assign V1_FLUSH = V1_FLUSH_FF_q;
   assign V2_FLUSH_FF_clk = PIXEL_CLK;
   assign V2_FLUSH_FF_ena = FLUSH_INTERNAL;
   assign V2_FLUSH_FF_clrn = !(cl_q == 3'b000);
   assign V2_FLUSH_FF_j = V_FLUSH_COUNTER_q == 9'b0_1000_1101;
   assign V2_FLUSH_FF_k = V_FLUSH_COUNTER_q == 9'b0_1110_0010;
   assign V2_FLUSH = V2_FLUSH_FF_q;

//  FLUSH_LINES_COUNTER KEEPS TRACK OF HOW MANY LINES ARE FLUSHED %
   assign flush_lines_counter0_clk_ctrl = V_FLUSH_COUNTER_q == 9'b0_1110_0011;
   assign flush_lines_counter0_ena_ctrl = FLUSH_INTERNAL;
   assign flush_lines_counter0_clrn_ctrl = !(cl_q == 3'b000);
   assign flush_lines_counter_d = flush_lines_counter_q + 12'b0000_0000_0001;
   assign FLUSH_DONE = flush_lines_counter_q == 12'b1010_0100_1110;

//  ****************************************************************
//  GRAYCODE COUNTER USED FOR HORIZONTAL LINE LENGTH COUNTER (INCREMENTED EACH PIXEL)
   assign H_ENABLE_FF_clk = PIXEL_CLK;
   assign H_ENABLE_FF_t = vcc;
   assign H_ENABLE_FF_clrn = (!(cl_q == 3'b000)) & (!(cl_q == 3'b111));
   assign H_XFER_COUNTER0_clk_ctrl = PIXEL_CLK;
   assign H_XFER_COUNTER0_ena_ctrl = cl_q == 3'b110;
   assign H_XFER_COUNTER0_clrn_ctrl = (!(cl_q == 3'b000)) & (!(cl_q ==
	 3'b111));
   assign H_XFER_COUNTER_t = {{H_XFER_COUNTER_q[10:0], H_ENABLE_FF_q} ==
	 12'b1000_0000_0001, {H_XFER_COUNTER_q[9:0], H_ENABLE_FF_q} ==
	 11'b100_0000_0001, {H_XFER_COUNTER_q[8:0], H_ENABLE_FF_q} ==
	 10'b10_0000_0001, {H_XFER_COUNTER_q[7:0], H_ENABLE_FF_q} ==
	 9'b1_0000_0001, {H_XFER_COUNTER_q[6:0], H_ENABLE_FF_q} ==
	 8'b1000_0001, {H_XFER_COUNTER_q[5:0], H_ENABLE_FF_q} == 7'b100_0001,
	 {H_XFER_COUNTER_q[4:0], H_ENABLE_FF_q} == 6'b10_0001,
	 {H_XFER_COUNTER_q[3:0], H_ENABLE_FF_q} == 5'b1_0001,
	 {H_XFER_COUNTER_q[2:0], H_ENABLE_FF_q} == 4'b1001,
	 {H_XFER_COUNTER_q[1:0], H_ENABLE_FF_q} == 3'b101,
	 {H_XFER_COUNTER_q[0], H_ENABLE_FF_q} == 2'b11, H_ENABLE_FF_q == 1'b0};


   always @(JMP3 or H_XFER_COUNTER_q) begin
      H_xfer_done_ff_clk = 1'bx;

//  H_XFER_DONE INDICATES THE END OF A LINE
      if (JMP3) begin
	 H_xfer_done_ff_clk = H_XFER_COUNTER_q == 12'b1011_0010_0100;
      end else begin
	 H_xfer_done_ff_clk = H_XFER_COUNTER_q == 12'b1011_0100_0010;
      end
   end
   assign H_xfer_done_ff_d = vcc;
   assign H_xfer_done_ff_clrn = (!(cl_q == 3'b001)) & (!(cl_q == 3'b111));
   assign H_xfer_done = H_xfer_done_ff_q;

//  ****************************************************************
//  VERTICAL LINE LENGTH COUNTER (INCREMENTED AT THE END OF EACH LINE)
   assign V_line_counter0_clk_ctrl = PIXEL_CLK;
   assign V_line_counter0_ena_ctrl = H_xfer_done;
   assign V_line_counter_d = V_line_counter_q + 12'b0000_0000_0001;
   assign V_line_counter0_clrn_ctrl = !(cl_q == 3'b000);


   always @(JMP3 or V_line_counter_q) begin
      frame_xfer_done_ff_clk = 1'bx;

//  FRAME_XFER_DONE INDICATES THE END OF A FRAME %
      if (JMP3) begin
	 frame_xfer_done_ff_clk = V_line_counter_q == 12'b1010_1010_0000;
      end else begin
	 frame_xfer_done_ff_clk = V_line_counter_q == 12'b1010_0001_1000;
      end
   end
   assign frame_xfer_done_ff_d = vcc;

// CHANGE "SETUP" TO "CLEAR_ALL" BY MZH
   assign frame_xfer_done_ff_clrn = !(cl_q == 3'b000);
   assign frame_xfer_done = frame_xfer_done_ff_q;

//  ****************************************************************
//  LINE RATE SIGNALS:
//  ****************************************************************
//  V1 AND V2 OUTPUT ACCORDING TO WHAT STATE THE CLOCKING STATE MACHINE IS IN (FLUSH OR V_TRANSFER)%
   assign V2_FF_clk = PIXEL_CLK;
   assign V2_FF_clrn = !(cl_q == 3'b001);
   assign V2_LINE = V2_FF_q;
   assign V1_FF_clk = PIXEL_CLK;
   assign V1_FF_clrn = !(cl_q == 3'b001);
   assign V1_LINE = V1_FF_q;


   always @(JMP3 or v_xfer_counter_q) begin
      {V2_FF_j, V2_FF_k, V1_FF_j, V1_FF_k} = 4'b0000;
      if (JMP3) begin
	 V2_FF_j = v_xfer_counter_q == 9'b0_1010_1001;
	 V2_FF_k = v_xfer_counter_q == 9'b0_1111_1110;
	 V1_FF_j = v_xfer_counter_q == 9'b0_0001_1110;
	 V1_FF_k = v_xfer_counter_q == 9'b0_1010_1100;
      end else begin
	 V2_FF_j = v_xfer_counter_q == 9'b0_1000_1101;
	 V2_FF_k = v_xfer_counter_q == 9'b0_1110_0010;
	 V1_FF_j = v_xfer_counter_q == 9'b0_0000_0010;
	 V1_FF_k = v_xfer_counter_q == 9'b0_1001_0000;
      end
   end
   assign V1_CLK = (V1_LINE & cl_q == 3'b101) | (V1_FLUSH & FLUSH_INTERNAL);
   assign V2_CLK = (V2_LINE & cl_q == 3'b101) | (V2_FLUSH & FLUSH_INTERNAL);

// ADD "#CLOCKING_SM==LINE_CHECK" BY MZH ON APRIL 9,OTHERWISE THE "FRAME" SIGNAL WILL NOT BE OK!
   assign FRAME_FF_clk = cl_q == 3'b110 | cl_q == 3'b111;
   assign FRAME_FF_clrn = !(cl_q == 3'b000);
   assign FRAME_FF_d = vcc;
   assign FRAME_OUT_FF_clk = PIX;

// added by mzh
   assign FRAME_OUT_FF_clrn = !(cl_q == 3'b000);
   assign FRAME_OUT_FF_d = FRAME_FF_q;
   assign FRAME = FRAME_OUT_FF_q;
   assign LINE_FF_clk = PIX;
   assign LINE_FF_clrn = !(cl_q == 3'b000);
   assign LINE_FF_j = H_XFER_COUNTER_q == 12'b0000_0000_1101;


   always @(JMP3 or v_xfer_counter_q) begin
      LINE_FF_k = 1'b0;
      if (JMP3) begin
	 LINE_FF_k = v_xfer_counter_q == 9'b0_0001_1100;
      end else begin
	 LINE_FF_k = v_xfer_counter_q == 9'b0_0000_0001;
      end
   end
   assign LINE = LINE_FF_q;
   assign PBLK_FF_clk = PIXEL_CLK;
   assign PBLK_FF_clrn = !(cl_q == 3'b000);


   always @(JMP3 or v_xfer_counter_q) begin
      {PBLK_FF_j, PBLK_FF_k} = 2'b00;
      if (JMP3) begin
	 PBLK_FF_j = v_xfer_counter_q == 9'b0_0001_1100;
	 PBLK_FF_k = v_xfer_counter_q == 9'b1_0000_1110;
      end else begin
	 PBLK_FF_j = v_xfer_counter_q == 9'b0_0000_0001;
	 PBLK_FF_k = v_xfer_counter_q == 9'b0_1111_0000;
      end
   end
   assign PBLK = !PBLK_FF_q;
   assign CLPOB1_ENA_FF_clk = PIXEL_CLK;
   assign CLPOB1_ENA_FF_clrn = !(cl_q == 3'b000);
   assign CLPOB1_ENA_FF_j = V_line_counter_q == 12'b0000_0000_0101;
   assign CLPOB1_ENA_FF_k = V_line_counter_q == 12'b0000_0000_1111;
   assign CLPOB1_FF_clk = PIXEL_CLK;
   assign CLPOB1_FF_clrn = !(cl_q == 3'b000);
   assign CLPOB1_FF_j = H_XFER_COUNTER_q == 12'b0000_1010_1100;
   assign CLPOB1_FF_k = H_XFER_COUNTER_q == 12'b1101_0010_0110;
   assign CLPOB1 = CLPOB1_FF_q;
   assign CLPOB2_FF_clk = PIXEL_CLK;
   assign CLPOB2_FF_clrn = !(cl_q == 3'b000);
   assign CLPOB2_FF_j = H_XFER_COUNTER_q == 12'b1011_1100_0111;
   assign CLPOB2_FF_k = H_XFER_COUNTER_q == 12'b1011_1100_0001;
   assign CLPOB2 = CLPOB2_FF_q;


   always @(DIO or CLPOB2 or CLPOB1 or CLPOB1_ENA_FF_q or vcc) begin
      CLPOB = 1'b0;
      casex (DIO[1:0])
      2'b00: begin
	    CLPOB = (!(CLPOB1 & CLPOB1_ENA_FF_q)) & (!(CLPOB2 &
		  (!CLPOB1_ENA_FF_q)));
	 end
      2'b01: begin
	    CLPOB = !CLPOB2;
	 end
      2'b10: begin
	    CLPOB = !(CLPOB1 & CLPOB1_ENA_FF_q);
	 end
      2'b11: begin
	    CLPOB = vcc;
	 end
      endcase
   end
   assign CLPDM_FF_clk = PIXEL_CLK;
   assign CLPDM_FF_clrn = !(cl_q == 3'b000);
   assign CLPDM_FF_j = H_XFER_COUNTER_q == 12'b1011_0100_0000;
   assign CLPDM_FF_k = H_XFER_COUNTER_q == 12'b1011_0100_0010;
   assign CLPDM = !CLPDM_FF_q;
   assign H2_CLK = PIXEL_CLK & (!(cl_q == 3'b101));
   assign H1_CLK = !H2_CLK;
   assign H1BR_CLK = !H2_CLK;

//  **************************************************************** 
//  THE CCD RESET CLOCK IS A FREE RUNNING CLOCK 
//  **************************************************************** 
   assign R_CLK = !DELAYED_PIXEL_CLK;

//  **************************************************************** 
//  THE AFE SHP SIGNAL (CDS CLAMP) IS A FREE RUNNING CLOCK 
//  **************************************************************** 
   assign SHD = !DELAYED_PIXEL_CLK;

//  **************************************************************** 
//  THE AFE SHD SIGNAL (CDS SAMPLE) IS A FREE RUNNING CLOCK 
//  **************************************************************** 
   assign SHP = DELAYED_PIXEL_CLK;

//  **************************************************************** 
//  THE AFE DATACLK SIGNAL IS A FREE RUNNING CLOCK 
//  **************************************************************** 
   assign DATACLK = DELAYED_PIXEL_CLK;

//  **************************************************************** 
//  PIXEL SYNC SIGNAL IS A FREE RUNNING CLOCK 
//  **************************************************************** 
   assign PIX = !DELAYED_PIXEL_CLK;

//  **************************************************************** 
//  Generate Integration clock 
//  **************************************************************** 
//  The integration counter is enabled when the Clocking state machine is   
//  in the INTEGRATE state, and is reset when the Clocking state machine is 
//  in the CLEAR state 
   assign integration_counter0_clk_ctrl = INTEGRATE_SYNC_q;

// USED TO BE INTEGRATE
   assign integration_counter0_ena_ctrl = EXT_INT_FF_q;
   assign integration_counter0_clrn_ctrl = !(cl_q == 3'b000);
   assign integration_counter_d = integration_counter_q + 16'h1;
   assign FLUSH1_FF_clk = FLUSH_DONE;
   assign FLUSH1_FF_d = vcc;
   assign FLUSH1_FF_clrn = !(cl_q == 3'b000);
   assign FLUSH_OK_FF_clk = INTEGRATE_SYNC_q;
   assign FLUSH_OK_FF_d = FLUSH1_FF_q;
   assign FLUSH_OK_FF_clrn = !(cl_q == 3'b000);
   assign FLUSH_OK = FLUSH_OK_FF_q;
   assign INTEGRATE_OK_FF_ena = cl_q == 3'b010;
   assign INTEGRATE_OK_FF_clk = INTEGRATE_SYNC_q;
   assign INTEGRATE_OK_FF_d = vcc;
   assign INTEGRATE_OK_FF_clrn = !(cl_q == 3'b100);
   assign INTEGRATE_OK = INTEGRATE_OK_FF_q;
   assign external_integrate_done_ff_clk = DIO[13];
   assign external_integrate_done_ff_d = vcc;
   assign external_integrate_done_ff_clrn = !(cl_q == 3'b000);
   assign internal_integrate_done_ff_clk = PIXEL_CLK;
   assign internal_integrate_done_ff_k = gnd;
   assign internal_integrate_done_ff_clrn = !(cl_q == 3'b000);
   assign integrate_done = (internal_integrate_done_ff_q & (!JMP2)) |
	 (external_integrate_done_ff_q & JMP2);


   always @(DIO or integration_counter_q) begin
      internal_integrate_done_ff_j = 1'b0;
      casex (DIO[10:6])
      5'b0_0000: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h1;
	 end
      5'b0_0001: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h2;
	 end
      5'b0_0010: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h3;
	 end
      5'b0_0011: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h4;
	 end
      5'b0_0100: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h5;
	 end
      5'b0_0101: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h7;
	 end
      5'b0_0110: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'hA;
	 end
      5'b0_0111: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'hE;
	 end
      5'b0_1000: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h13;
	 end
      5'b0_1001: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h17;
	 end
      5'b0_1010: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h27;
	 end
      5'b0_1011: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h43;
	 end
      5'b0_1100: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h59;
	 end
      5'b0_1101: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h64;
	 end
      5'b0_1110: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h7D;
	 end
      5'b0_1111: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h96;
	 end
      5'b1_0000: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'hBD;
	 end
      5'b1_0001: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'hC8;
	 end
      5'b1_0010: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'hFA;
	 end
      5'b1_0011: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h12C;
	 end
      5'b1_0100: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h142;
	 end
      5'b1_0101: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h190;
	 end
      5'b1_0110: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h1E9;
	 end
      5'b1_0111: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h2E3;
	 end
      5'b1_1000: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h3DD;
	 end
      5'b1_1001: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h5D1;
	 end
      5'b1_1010: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h7C5;
	 end
      5'b1_1011: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h137D;
	 end
      5'b1_1100: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h2705;
	 end
      5'b1_1101: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h3A8D;
	 end
      5'b1_1110: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'h7525;
	 end
      5'b1_1111: begin
	    internal_integrate_done_ff_j = integration_counter_q == 16'hEA55;
	 end
      endcase
   end

//  *************************************************************************** 
//  *************************************************************************** 
//  *************************************************************************** 
//  The following section is a subdesign block used to control the generation   
//  of the 3 wire serial interface.                                             
//  SCLOCK and SLOAD are generated here, as well as the necessary               
//  clocks for the serial clock state machine and the load signal for the 74165 
//  *************************************************************************** 
//  GENERATE THE SERIAL RATE CLOCK FROM THE PIXEL CLOCK 
//  MAXIMUM SERIAL CLOCK OPERATING RATE IS 10 MHZ 
//  DIVIDE PIXEL CLOCK BY 8 TO INSURE NO PROBLEMS (DIVIDE BY 4 HERE, PLUS DIVIDE BY TWO AT SCLOCK FF
   assign SER_CLK_FF1_clk = PIXEL_CLK;
   assign SER_CLK_FF1_t = vcc;
   assign SER_CLK_FF2_clk = SER_CLK_FF1_q;
   assign SER_CLK_FF2_t = vcc;
   assign SER_CLK = SER_CLK_FF2_q;

//  ************************************************************************ 
//  power_on_clear is a signal that indicates that the circuit board has been reset 
//  On the rising edge of this signal, the serial loading of the delay IC's is  
//  enabled AFTER A MINIMUM DELAY OF 15MS. 
//  MUST ADD A DELAY OF AT LEAST 15MS HERE, USE INT_CLK, 3 UNIT INTEGRATE CYCLES
   assign DELAY_SLOAD_COUNTER0_clrn_ctrl = (!power_on_clear) &
	 (!SLOAD_ENABLE_FF_q);
   assign DELAY_SLOAD_COUNTER0_clk_ctrl = INTEGRATE_SYNC_q;
   assign DELAY_SLOAD_COUNTER_d = DELAY_SLOAD_COUNTER_q + 2'b01;
   assign SLOAD_ENABLE_FF_clrn = !power_on_clear;
   assign SLOAD_ENABLE_FF_clk = DELAY_SLOAD_COUNTER_q == 2'b11;
   assign SLOAD_ENABLE_FF_d = vcc;
   assign SLOAD_OK_FF_clk = SLOAD_ENABLE_FF_q;
   assign SLOAD_OK_FF_d = vcc;
   assign SLOAD_OK_FF_clrn = !(sclk_q == 4'b1011);

//  SERIAL INTERFACE SECTION 
//  CLEAR THE SERIAL INTERFACE COUNTER AT THE END OF EACH TASK 
   assign SCOUNTER_CLR_FF_clk = sclk_q == 4'b1011;
   assign SCOUNTER_CLR_FF_d = vcc;
   assign SCOUNTER_CLR_FF_clrn = !SER_COUNTER_CLEAR;
   assign CLEAR_SCOUNTER_FF1_clk = AFE_q == 5'b1_0010;
   assign CLEAR_SCOUNTER_FF1_d = vcc;
   assign CLEAR_SCOUNTER_FF1_clrn = !SER_COUNTER_CLEAR;
   assign CLEAR_SCOUNTER_FF2_clk = PIXEL_CLK;
   assign CLEAR_SCOUNTER_FF2_d = SCOUNTER_CLR_FF_q | CLEAR_SCOUNTER_FF1_q;
   assign SER_COUNTER_CLEAR = CLEAR_SCOUNTER_FF2_q;

//  ************************************************************************ 
//  SERIAL INTERFACE ENABLE SECTION 
//  serial_ena is an active HIGH signal used to enable the loading of information 
//  into the DELAY IC'S from either the PLD or external digital inputs 
   assign DEFAULT_DELAY_FF_clk = SLOAD_OK_FF_q;
   assign DEFAULT_DELAY_FF_d = vcc;
   assign DEFAULT_DELAY_FF_clrn = (!(sclk_q == 4'b1011)) & (!power_on_clear);
   assign DEFAULT_AFE_FF_clk = sclk_q == 4'b1011;
   assign DEFAULT_AFE_FF_d = vcc;
   assign DEFAULT_AFE_FF_clrn = (!(AFE_q == 5'b1_0010)) & (!power_on_clear);
   assign SERIAL_ENA = DEFAULT_DELAY_FF_q | DEFAULT_AFE_FF_q;

//  ************************************************************************ 
//  Control_clk is a counter.  The signals needed to serial load the delay IC's 
//  are generated on fixed counts of this counter. The counter, as well as      
//  the SLOAD_OK_FF that enables it, are cleared at the end of the loading   
//  process 
   assign control_clk0_clk_ctrl = SER_CLK;
   assign control_clk0_ena_ctrl = DEFAULT_DELAY_FF_q | DEFAULT_AFE_FF_q;
   assign control_clk0_clrn_ctrl = (!power_on_clear) & (!SER_COUNTER_CLEAR);
   assign control_clk_d = control_clk_q + 6'b00_0001;

//  ************************************************************************ 
//  Update_byte is a signal is used to clock the DEFAULT DELAY state machine 
   assign update_ff_clrn = !power_on_clear;
   assign update_ff_clk = SER_CLK;
   assign update_ff_d = control_clk_q == 6'b00_0100 | control_clk_q ==
	 6'b01_1100;
   assign update_byte = update_ff_q;

//  ************************************************************************ 
//  load_byte is a signal used to load a byte of information into the 74165 
   assign load_ff_clrn = !power_on_clear;
   assign load_ff_clk = SER_CLK;
   assign load_ff_d = control_clk_q == 6'b00_0111 | control_clk_q ==
	 6'b01_1111;
   assign load_byte = !load_ff_q;

//  ************************************************************************ 
//  SLOAD is an active HIGH signal used to enable the loading of information into the DELAY LINES 
   assign SLOAD_DELAY_FF_clk = SER_CLK;
   assign SLOAD_DELAY_FF_ena = DEFAULT_DELAY_FF_q;
   assign SLOAD_DELAY_FF_clrn = !power_on_clear;
   assign SLOAD_DELAY_FF_j = control_clk_q == 6'b00_0101;
   assign SLOAD_DELAY_FF_k = sclk_q == 4'b0101 & control_clk_q == 6'b11_1100;
   assign SLOAD = SLOAD_DELAY_FF_q;

//  ************************************************************************ 
//  CH1_SLOAD is an active LOW signal used to enable the loading of information AFE1 
//  CH2_SLOAD is an active LOW signal used to enable the loading of information AFE2 
   assign SLOAD_AFE_FF_clk = SER_CLK;
   assign SLOAD_AFE_FF_ena = DEFAULT_AFE_FF_q;
   assign SLOAD_AFE_FF_clrn = (!(AFE_q == 5'b1_0010)) & (!power_on_clear);
   assign SLOAD_AFE_FF_j = control_clk_q == 6'b00_0101;
   assign SLOAD_AFE_FF_k = control_clk_q == 6'b11_1100;
   assign CH1_SLOAD = !SLOAD_AFE_FF_q;
   assign CH2_SLOAD = CH1_SLOAD;

//  ************************************************************************
//  sclock is the serial clock used to clock information into the DELAY IC'S
   assign sclock_ff_clk = SER_CLK;
   assign sclock_ff_clrn = !power_on_clear;
   assign sclock_ff_d = control_clk_q == 6'b00_1010 | control_clk_q ==
	 6'b00_1100 | control_clk_q == 6'b00_1110 | control_clk_q == 6'b01_0000
	 | control_clk_q == 6'b01_0010 | control_clk_q == 6'b01_0100 |
	 control_clk_q == 6'b01_0110 | control_clk_q == 6'b01_1000 |
	 control_clk_q == 6'b10_0010 | control_clk_q == 6'b10_0100 |
	 control_clk_q == 6'b10_0110 | control_clk_q == 6'b10_1000 |
	 control_clk_q == 6'b10_1010 | control_clk_q == 6'b10_1100 |
	 control_clk_q == 6'b10_1110 | control_clk_q == 6'b11_0000;
   assign SCLOCK = sclock_ff_q;

//  ************************************************************************
   assign FF_BIT0_clk_ctrl = update_byte;
   assign bit = FF_BIT_q;
   assign sclk0_clr_ctrl = power_on_clear;
   assign sclk0_clk_ctrl = update_byte;


   always @(sclk_q) begin
      sclk_d = sclk_q;
      {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
	    FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0000_0000;
      casex (sclk_q)
      4'b0000: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0000_0000;
	    sclk_d = 4'b1010;
	 end
      4'b1010: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0010_0000;
	    sclk_d = 4'b0111;
	 end
      4'b0111: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0010_1010;
	    sclk_d = 4'b0110;
	 end
      4'b0110: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0011_0000;
	    sclk_d = 4'b1001;
	 end
      4'b1001: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0000_0000;
	    sclk_d = 4'b1000;
	 end
      4'b1000: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0001_0000;
	    sclk_d = 4'b0001;
	 end
      4'b0001: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0001_0000;
	    sclk_d = 4'b0010;
	 end
      4'b0010: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0001_0000;
	    sclk_d = 4'b0011;
	 end
      4'b0011: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0001_0000;
	    sclk_d = 4'b0100;
	 end
      4'b0100: begin
	    {FF_BIT7_d_1, FF_BIT6_d_1, FF_BIT5_d_1, FF_BIT4_d_1, FF_BIT3_d_1,
		  FF_BIT2_d_1, FF_BIT1_d_1, FF_BIT0_d_1} = 8'b0001_1110;
	    sclk_d = 4'b0101;
	 end
      4'b0101: begin
	    sclk_d = 4'b1011;
	 end
      4'b1011: begin

//  The state machine is now done, DELAYS programmed
	    sclk_d = 4'b1011;
	 end
      endcase
   end
   assign AFE0_ena_ctrl = sclk_q == 4'b0101 | sclk_q == 4'b1011;
   assign AFE0_clr_ctrl = power_on_clear;
   assign AFE0_clk_ctrl = update_byte;


   always @(AFE_q) begin
      AFE_d = AFE_q;
      {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
	    FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0000_0000;
      casex (AFE_q)
      5'b0_0000: begin
	    AFE_d = 5'b0_0001;
	 end
      5'b0_0001: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0000_0100;
	    AFE_d = 5'b0_0010;
	 end
      5'b0_0010: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0000_1000;
	    AFE_d = 5'b0_0011;
	 end
      5'b0_0011: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0100_0110;
	    AFE_d = 5'b0_0100;
	 end
      5'b0_0100: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1000_0100;
	    AFE_d = 5'b0_0101;
	 end
      5'b0_0101: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0010_0000;
	    AFE_d = 5'b0_0110;
	 end
      5'b0_0110: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1001_1000;
	    AFE_d = 5'b0_0111;
	 end
      5'b0_0111: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0110_0010;
	    AFE_d = 5'b0_1000;
	 end
      5'b0_1000: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1000_0000;
	    AFE_d = 5'b0_1001;
	 end
      5'b0_1001: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0001_0110;
	    AFE_d = 5'b0_1010;
	 end
      5'b0_1010: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1010_0000;
	    AFE_d = 5'b0_1011;
	 end
      5'b0_1011: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0101_0110;
	    AFE_d = 5'b0_1100;
	 end
      5'b0_1100: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1010_0000;
	    AFE_d = 5'b0_1101;
	 end
      5'b0_1101: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0011_0110;
	    AFE_d = 5'b0_1110;
	 end
      5'b0_1110: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1010_0000;
	    AFE_d = 5'b0_1111;
	 end
      5'b0_1111: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b0111_0110;
	    AFE_d = 5'b1_0000;
	 end
      5'b1_0000: begin
	    {FF_BIT7_d_2, FF_BIT6_d_2, FF_BIT5_d_2, FF_BIT4_d_2, FF_BIT3_d_2,
		  FF_BIT2_d_2, FF_BIT1_d_2, FF_BIT0_d_2} = 8'b1010_0000;
	    AFE_d = 5'b1_0001;
	 end
      5'b1_0001: begin
	    AFE_d = 5'b1_0010;
	 end
      5'b1_0010: begin

//  THE STATE MACHINE IS NOW DONE, AFE REGISTERS PROGRAMMED
	    AFE_d = 5'b1_0010;
	 end
      endcase
   end


// Assignments added to explicitly combine the
// effects of multiple drivers in the source
   assign FF_BIT_d[0] = FF_BIT0_d_1 | FF_BIT0_d_2;
   assign FF_BIT_d[1] = FF_BIT1_d_1 | FF_BIT1_d_2;
   assign FF_BIT_d[2] = FF_BIT2_d_1 | FF_BIT2_d_2;
   assign FF_BIT_d[3] = FF_BIT3_d_1 | FF_BIT3_d_2;
   assign FF_BIT_d[4] = FF_BIT4_d_1 | FF_BIT4_d_2;
   assign FF_BIT_d[5] = FF_BIT5_d_1 | FF_BIT5_d_2;
   assign FF_BIT_d[6] = FF_BIT6_d_1 | FF_BIT6_d_2;
   assign FF_BIT_d[7] = FF_BIT7_d_1 | FF_BIT7_d_2;

// Define power signal(s)
   assign vcc = 1'b1;
   assign gnd = 1'b0;
endmodule
